library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity unsigned_comperator is
	generic (
		size				: positive
	);
	port(
		op1		: in  std_logic_vector(size-1 downto 0);
		op2		: in  std_logic_vector(size-1 downto 0);

		greater	: out std_logic
	);
end entity;

architecture behaviour of unsigned_comperator is
begin
	process(op1, op2) begin
		if (op1 > op2) then
			greater <= '1';
		else
			greater <= '0';
		end if;
	end process;
end architecture;